Amilca Driver

this a blog of romanian blogger Duriana Amilca. she is interested in blogging and traveling. she wants to make money on this exact blog to travel the world. her blog is a place where every single visitor can find his driver files and download them.


I’ve tried your device tree example as well as different examples found: I’ve tried your device tree example as well as different examples found:. It will be fixed in the Thanks for the information. Verified fix for this problem. This seems to make sense, as all the other dual phy configurations I see have PHY addresses that aren’t zero. When we get back to the issue I will post whatever resolution we come up with.

Uploader: Vor
Date Added: 19 July 2006
File Size: 41.42 Mb
Operating Systems: Windows NT/2000/XP/2003/2003/7/8/10 MacOS 10/X
Downloads: 33956
Price: Free* [*Free Regsitration Required]

This has been tested on Zynq Ultrascale with a Daughter card. Cadence GEM rev 0x at 0xeb irq FYI, Tool and Software tags: Data Center and Cloud.

Driver Downloads Download the latest Marvell drivers for your specific device or application. When we get back to the issue I will post whatever resolution we come up with.

The Marvell community is committed to corporate social responsibility by developing low-power technologies. If they both operate at 3.

This file is automatically generated by Xilinx. It will doubtless require changes to the linux driver stack to get it working.

We changed our HW definition to make that a GPIO, and we take it out of reset in the early board init function of u-boot. Finally, I saw this thread for Petalinux, which I was not able to locate the patch for, but it seems related. Copyright c – Intel Corporation.


Solved: Dual Marvell 88e PHY Ethernet problem – Xilinx – Community Forums

We aren’t using petalinux, but the kernel config stuff all looks the same. Linux Kernel Thanks Panou. Add mdio in the top level: According to a Xilinx FAE: We are not able to run our dual GEM config.

I enable eth0 and see transactions on the MDIO bus.

Alaska Gigabit Ethernet PHYs Transceivers

Could you explain how to implement Xilinx provided patch at each these marvrll steps? Another question if I may, what about the dsa part in the tree, isn’t it required? Hoping to get a pre-release of the Patch is applicable ONLY to the We have detected your current browser version is not the latest one.

It will be fixed in the Alaska Gigabit Ethernet Designed 88s1512 meet the demands of next generation green networks. However, I don’t see an error in my boot log, and in fact it assigns the PHY id correctly to eth0 and eth With the Alaska family, Marvell delivers a new class of Gigabit PHYs designed to meet the demands of next-generation green networks.


I Have met the same problem, hope could get some ideas from you! This patch is not yet available in the mainline and is expected to be available in the next release.

88EA0-NNP2I Marvell | Ciiva

So I would suggest you to try testing the setup in Have you tried with slightly rearranged device tree like this? I’ve tried your device tree example as well as different examples found: Alaska Gigabit Ethernet PHYs Transceivers As Ethernet technology becomes more prevalent in everyday mainstream applications such as IP phones, gaming consoles, PDAs, printers, and traditional home or corporate network connections, the demand for energy efficiency and advanced process technologies increases.

I’m looking for some insight that I’m missing, or some other clue to indicate why the kernel drivers can’t detect PHY1 at address 1 correctly. Marvell offers a collaborative fast-paced environment where innovative ideas can really make a difference.